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tc59lm913/05amb-50,-55 2004-08-20 1/52 rev 1.0 tentative toshiba mos digital integr ated circuit silicon monolithic 512mbits network fcram1 (sstl_2 interface) ? 4,194,304-words 8 banks 16-bits ? 8,388,608-words 8 banks 8-bits description network fcram tm is double data rate fast cycle random access memory. tc59lm913/05amb is network fcram tm containing 536,870,912 memory cells. tc59l m913amb is organized as 4,194,304-words 8 banks 16 bits, TC59LM905AMB is organized as 8,388,608-words 8 banks 8 bits. tc59lm913/05amb feature a fully synchronous operation referenced to cl ock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. tc59lm913/05amb can operate fast core cycle compared with regular ddr sdram. tc59lm913/05amb is suitable for networ k, server and other applications where large memory density and low power consumption are re quired. the output dr iver for network fcram tm is capable of high quality fast data transfer under light loading condition. features tc59lm913/05 parameter -50 -55 cl = 3 5.5 ns 6.0 ns t ck clock cycle time (min) cl = 4 5.0 ns 5.5 ns t rc random read/write cycle time (min) 25.0 ns 27.5 ns t rac random access time (max) 22.0 ns 24.0 ns i dd1s operating current (singl e bank) (max) 240 ma 225 ma l dd2p power down current (max) 80 ma 75 ma l dd6 self-refresh current (max) 20 ma 20 ma ? fully synchronous operation ? double data rate (ddr) data input/output are synchroniz ed with both edges of dqs. ? differential clock (clk and clk ) inputs cs , fn and all address input signals are sampled on the positive edge of clk. output data (dqs and dqs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 5 ns minimum clock: 200 mhz maximum data: 400 mbps/pin maximum ? fast cycle and short latency ? eight independent banks operation when ba2 input assign to a14 input, tc59lm913/05amb can function as 4bank device (keep backward compatibility to 256mb) ? bidirectional data strobe signal ? distributed auto-refresh cycle in 3.9 s ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length cas latency = 3, 4 burst length = 2, 4 ? organization: tc59lm913amb : 4,194,304 words 8 banks 16 bits TC59LM905AMB : 8,388,608 words 8 banks 8 bits ? power supply voltage v dd : 2.5 v 0.15v v ddq : 2.5 v 0.15 v ? 2.5 v cmos i/o comply with sstl_2 (half strength driver) ? package: 60ball bga, 1mm 1mm ball pitch (p ? bga64 ? 1317 ? 1.00az) ? keep backward compatibility for tc59lm814/06cft(256mbits) except package design. notice : fcram is trademark of fujitsu limited, japan.
tc59lm913/05amb-50,-55 2004-08-20 2/52 rev 1.0 TC59LM905AMB pin names pin names pin names a0~a13 address input dqs write/read data strobe ba0~ba2 bank address v dd power ( + 2.5 v) dq0~dq7 data input / output v ss ground cs chip select v ddq power ( + 2.5 v) (for i/o buffer) fn function control v ssq ground (for i/o buffer) pd power down control v ref reference voltage clk, clk clock input nc not connected 4 bank operation can be performed using ba2 as a14. pin assignment (top view) : depopulated ball ball pitch=1.0 x 1.0mm 5 a b c d e f g h j k 1 3 6 4 2 x 8 l m n p r nc nc nc nc v dd nc dq1 nc nc dq3 nc nc ba2 a13 nc ba0 a10 a1 v dd v ss nc dq6 nc nc dq4 nc nc vref clk a12 a11 a8 a5 v ss dq7 v ss q v dd q dq5 v ss q v dd q v ss q v ss clk pd a9 a7 a6 a4 dq0 v dd q v ss q dq2 v dd q v ss q v dd q v dd fn cs ba1 a0 a2 a3 nc dqs inde x
tc59lm913/05amb-50,-55 2004-08-20 3/52 rev 1.0 tc59lm913amb pin names pin name pin name a0~a13 address input udqs/ldqs write/read data strobe ba0~ba2 bank address v dd power ( + 2.5 v) dq0~dq15 data input/output v ss ground cs chip select v ddq power ( + 2.5 v) (for i/o buffer) fn function control v ssq ground (for i/o buffer) pd power down control v ref reference voltage clk, clk clock input nc not connected 4 bank operation can be performed using ba2 as a14. pin assignment (top view) : depopulated ball ball pitch=1.0 x 1.0mm 5 a b c d e f g h j k 1 3 6 4 2 x 16 l m n p r nc nc nc nc v dd dq1 dq2 dq3 dq5 dq6 dq7 nc ba2 a13 nc ba0 a10 a1 v dd v ss dq14 dq13 dq12 dq10 dq9 dq8 nc vref clk a12 a11 a8 a5 v ss dq15 v ss q v dd q dq11 v ss q v dd q v ss q v ss clk pd a9 a7 a6 a4 dq0 v dd q v ss q dq4 v dd q v ss q v dd q v dd fn cs ba1 a0 a2 a3 ldqs udqs inde x
tc59lm913/05amb-50,-55 2004-08-20 4/52 rev 1.0 block diagram note: the TC59LM905AMB configuration is 8 bank of 16384 512 8 of cell array with the dq pins numbered dq0~dq7. the tc59lm913amb configuration is 8 bank of 16384 256 16 of cell array with the dq pins numbered dq0~dq15. dq0~dqn dll clock buffer cl k clk pd to each block command decoder cs fn address buffer control signal generator mode register refresh counter a0~a13 ba0~ba2 burst counter write address latch/ address comparator data control and latch circuit upper address latch read data buffer dq buffer dqs lower address latch write data buffer bank #7 bank #6 bank #5 bank #4 bank #3 bank #2 bank #1 bank #0 memory cell array column decoder row decoder
tc59lm913/05amb-50,-55 2004-08-20 5/52 rev 1.0 absolute maximum ratings symbol parameter rating unit notes v dd power supply voltage ? 0.3~3.3 v v ddq power supply voltage (for i/o buffer) ? 0.3~v dd + 0.3 v v in input voltage ? 0.3~v dd + 0.3 v v out output and i/o pin voltage ? 0.3~v ddq + 0.3 v v ref input reference voltage ? 0.3~v dd + 0.3 v t case operating temperature (case) 0~85 c t stg storage temperature ? 55~150 c t solder soldering temperature (10 s) 260 c p d power dissipation 2 w i out short circuit output current 50 ma caution: conditions outside the limits listed under ?absolute m aximum ratings? may cause permanent damage to the device. the device is not meant to be operated under conditions outside the limits descri bed in the operational section of this specification. exposure to ?absolute maximum ratings? conditions for extended periods may af fect device reliability. recommended dc, ac operating conditions (notes: 1)(t case = 0~85c) symbol parameter min typ. max unit notes v dd power supply voltage 2.35 2.5 2.65 v v ddq power supply voltage (for i/o buffer) 2.35 v dd v dd v v ref input reference voltage v ddq /2 96% v ddq /2 v ddq /2 104% v 2 v ih (dc) input dc high voltage v ref + 0.2 ? v ddq + 0.2 v 5 v il (dc) input dc low voltage ? 0.1 ? v ref ? 0.2 v 5 v ick (dc) differential clock dc input voltage ? 0.1 ? v ddq + 0.1 v 10 v id (dc) input differential voltage. clk and clk inputs (dc) 0.4 ? v ddq + 0.2 v 7, 10 v ih (ac) input ac high voltage v ref + 0.35 ? v ddq + 0.2 v 3, 6 v il (ac) input ac low voltage ? 0.1 ? v ref ? 0.35 v 4, 6 v id (ac) input differential voltage. clk and clk inputs (ac) 0.7 ? v ddq + 0.2 v 7, 10 v x (ac) differential ac input cross point voltage v ddq /2 ? 0.2 ? v ddq /2 + 0.2 v 8, 10 v iso (ac) differential clock ac middle level v ddq /2 ? 0.2 ? v ddq /2 + 0.2 v 9, 10
tc59lm913/05amb-50,-55 2004-08-20 6/52 rev 1.0 note: (1) all voltages referenced to v ss , v ssq . (2) v ref is expected to track variations in v ddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% v ref (dc). (3) overshoot limit: v ih (max) = v ddq + 0.9 v with a pulse width 5 ns. (4) undershoot limit: v il (min) = ? 0.9 v with a pulse width 5 ns. (5) v ih (dc) and v il (dc) are levels to mainta in the current logic state. (6) v ih (ac) and v il (ac) are levels to change to the new logic state. (7) v id is magnitude of the differen ce between clk input level and clk input level. (8) the value of v x (ac) is expected to equal v ddq /2 of the transmitting device. (9) v iso means {v ick (clk) + v ick ( clk )} /2 (10) refer to the figure below. (11) in the case of external term ination, vtt (termination voltage) should be gone in the range of v ref (dc) 0.04 v. capacitance (v dd = 2.5v , v ddq = 2.5 v, f = 1 mhz, ta = 25c) symbol parameter min max delta unit c in input pin capacitance 1.5 2.5 0.25 pf c inc clock pin (clk, clk ) capacitance 1.5 2.5 0.25 pf c i/o dq, dqs, udqs, ldqs capacitance 2.5 4.0 0.5 pf c nc nc pin capacitance ? 4.0 ? pf note: these parameters are periodi cally sampled and not 100% tested. v iso ( min ) v iso ( max ) v ick v ick v x v x v x v x v x v ick v ick cl k clk v ss |v id (ac)| 0 v differential v iso v ss v id (ac)
tc59lm913/05amb-50,-55 2004-08-20 7/52 rev 1.0 recommended dc operating conditions (v dd = 2.5v 0.15v, v ddq = 2.5v 0.15v, t case = 0~85c) max symbol parameter -50 -55 unit notes i dd1s operating current t ck = min, i rc = min ; read/write command cycling ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; 1 bank operation, burst length = 4 ; address change up to 2 times during minimum i rc . 240 225 1, 2 i dd2n standby current t ck = min, cs = v ih , pd = v ih ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; all banks: inactive state ; other input signals are changed one time during 4 t ck . 100 95 1, 2 i dd2p standby (power down) current t ck = min, cs = v ih , pd = v il (power down) ; 0 v v in v ddq ; all banks: inactive state 80 75 1, 2 i dd4w write operation current (4 banks) 8 bank interleaved continuous burst write operation ; t ck = min, i rc = min ; burst length = 4, cas latency = 4 ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; dq and dqs inputs change twice per clock cycle 350 330 1, 2 i dd4r read operation current (4 banks) 8 bank interleaved contio us burst read operation ; t ck = min, i rc = min, i out = 0ma ; burst length = 4, cas latency = 4 ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change once per clock cycle. read data change twice per clock cycle. 350 330 1, 2 i dd5b burst auto refresh current refresh command at every i refc interval ; t ck = min, i refc = min ; cas latency = 4 ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change up to 2 times during minimum i refc . dq and dqs inputs change twice per clock cycle. 250 240 1, 2, 3 i dd6 self-refresh current self-refresh mode ; pd = 0.2 v, 0 v v in v ddq 20 20 ma 2 notes: 1. these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters defines the current between v dd and v ss . 3. i dd5b is specified under burst refresh condition. actual system should use distributed refresh that meet t refi specification.
tc59lm913/05amb-50,-55 2004-08-20 8/52 rev 1.0 recommended dc operating conditions (continued) (v dd = 2.5v 0.15v, v ddq = 2.5v 0.15v, t case = 0~85c) symbol parameter min max unit notes i li input leakage current ( 0 v v in v ddq , all other pins not under test = 0 v) ? 5 5 a i lo output leakage current (output disabled, 0 v v out v ddq ) ? 5 5 a i ref v ref current ? 5 5 a i oh (dc) output source dc current v oh = v ddq ? 0.4v ? 10 ? i ol (dc) normal output driver output sink dc current v ol = 0.4v 10 ? i oh (dc) output source dc current v oh = v ddq ? 0.4v ? 11 ? i ol (dc) strong output driver output sink dc current v ol = 0.4v 11 ? i oh (dc) output source dc current v oh = v ddq ? 0.4v ? 8 ? i ol (dc) weaker output driver output sink dc current v ol = 0.4v 8 ? i oh (dc) output source dc current v oh = v ddq ? 0.4v ? 7 ? i ol (dc) weakest output driver output sink dc current v ol = 0.4v 7 ? ma 1 notes: 1. refer to output driver characteristics for the detail. output driver strength is selected by extended mode register.
tc59lm913/05amb-50,-55 2004-08-20 9/52 rev 1.0 ac characteristics and operating conditions (notes: 1, 2) (v dd = 2.5v 0.15v, v ddq = 2.5v 0.15v, t case = 0~85c) -50 -55 symbol parameter min max min max unit notes t rc random cycle time 25 ? 27.5 ? 3 c l = 3 5.5 8.5 6.0 12.0 3 t ck clock cycle time c l = 4 5.0 8.5 5.5 12.0 3 t rac random access time ? 22.0 ? 24.0 3 t ch clock high time 0.45 t ck ? 0.45 t ck ? 3 t cl clock low time 0.45 t ck ? 0.45 t ck ? 3 t ckqs qs access time from clk ? 0.65 0.65 ? 0.75 0.75 3, 8 t qsq data output skew from dqs ? 0.4 ? 0.45 4 t ac data access time from clk ? 0.65 0.65 ? 0.75 0.75 3, 8 t oh data output hold time from clk ? 0.65 0.65 ? 0.75 0.75 3, 8 t qspre dqs (read) preamble pulse width 0.9 t ck ? 0.2 1.1 t ck + 0.2 0.9 t ck ? 0.2 1.1 t ck + 0.2 3, 8 t hp clk half period (minimum of actual t ch , t cl ) min(t ch , t cl ) ? min(t ch , t cl ) ? 3 t qsp dqs (read) pulse width t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qsqv data output valid time from dqs t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qhs dq hold skew factor ? 0.55 ? 0.6 t dqss dqs (write) low to high setup time 0.75 t ck 1.25 t ck 0.75 t ck 1.25 t ck 3 t dspre dqs (write) preamble pulse width 0.4 t ck ? 0.4 t ck ? 4 t dspres dqs first input setup time 0 ? 0 ? 3 t dspreh dqs first low input hold time 0.25 t ck ? 0.25 t ck ? 3 t dsp dqs high or low input pulse width 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 4 c l = 3 1.3 ? 1.4 ? 3, 4 t dss dqs input falling edge to clock setup time c l = 4 1.3 ? 1.4 ? 3, 4 t dspst dqs (write) postamble pulse width 0.45 t ck ? 0.45 t ck ? 4 c l = 3 1.3 ? 1.4 ? 3, 4 t dspsth dqs (write) postamble hold time c l = 4 1.3 ? 1.4 ? 3, 4 t dssk udqs ? ldqs skew ( 16) ? 0. 5 t ck 0. 5 t ck ? 0. 5 t ck 0. 5 t ck t ds data input setup time from dqs 0.5 ? 0.5 ? 4 t dh data input hold time from dqs 0.5 ? 0.5 ? 4 t is command/address input setup time 0.9 ? 0.9 ? 3 t ih command/address input hold time 0.9 ? 0.9 ? ns 3
tc59lm913/05amb-50,-55 2004-08-20 10/52 rev 1.0 ac characteristics and operating conditions (notes: 1, 2) (continued) -50 -55 symbol parameter min max min max unit notes t lz data-out low impedance time from clk ? 0.65 ? ? 0.75 ? 3,6,8 t hz data-out high impedance time from clk ? 0.65 ? 0.75 3,7,8 t qslz dqs-out low impedance time from clk ? 0.65 ? ? 0.75 ? 3,6,8 t qshz dqs-out high impedance time from clk ? 0.65 0.65 ? 0.75 0.75 3,7,8 t qpdh last output to pd high hold time 0 ? 0 ? t pdex power down exit time 0.9 ? 0.9 ? 3 t t input transition time 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry ? 0.5 t ck 5 ? 0.5 t ck 5 ns 3 t refi auto-refresh average interval 0.4 3.9 0.4 3.9 5 t pause pause time after power-up 200 ? 200 ? s c l = 3 5 ? 5 ? i rc random read/write cycle time (applicable to same bank) c l = 4 5 ? 5 ? i rcd rda/wra to lal command input delay (applicable to same bank) 1 1 1 1 c l = 3 4 ? 4 ? i ras lal to rda/wra command input delay (applicable to same bank) c l = 4 4 ? 4 ? i rbd random bank access delay (applicable to other bank) 2 ? 2 ? b l = 2 2 ? 2 ? i rwd lal following rda to wra delay (applicable to other bank) b l = 4 3 ? 3 ? i wrd lal following wra to rda delay (applicable to other bank) 1 ? 1 ? c l = 3 5 ? 5 ? i rsc mode register set cycle time c l = 4 5 ? 5 ? i pd pd low to inactive state of input buffer ? 1 ? 1 i pda pd high to active state of input buffer ? 1 ? 1 c l = 3 15 ? 15 ? i pdv power down mode valid from ref command c l = 4 18 ? 18 ? c l = 3 15 ? 15 ? i refc auto-refresh cycle time c l = 4 18 ? 18 ? i ckd ref command to clock input disable at self-refresh entry 16 ? 16 ? i lock dll lock-on time (applicable to rda command) 200 ? 200 ? cycle
tc59lm913/05amb-50,-55 2004-08-20 11/52 rev 1.0 ac test conditions symbol parameter value unit notes v ih (min) input high voltage (minimum) v ref + 0.35 v v il (max) input low voltage (maximum) v ref ? 0.35 v v ref input reference voltage v ddq /2 v v tt termination voltage v ref v v swing input signal peak to peak swing 1.0 v vr differential clock input reference level v x (ac) v v id (ac) input differential voltage 1.5 v slew input signal minimum slew rate 1.0 v/ns v otr output timing measurement reference voltage v ddq /2 v 9 note: (1) transition times ar e measured between v ih min (dc) and v il max (dc). transition (rise and fall) of in put signals have a fixed slope. (2) if the result of nominal calculation with regard to t ck contains more than one de cimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75 t ck , t ck = 5 ns, 0.75 5 ns = 3.75 ns is rounded up to 3.8 ns.) (3) these parameters are measured fr om the differential clock (clk and clk ) ac cross point. (4) these parameters are measured from si gnal transition point of ds crossing v ref level. (5) the t refi (max) applies to equally distributed refresh method. the t refi (min) applies to both burst refresh meth od and distributed refresh method. in such case, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. (6) low impedance state is specified at v ddq /2 0.2 v from steady state. (7) high impedance state is specified wh ere output buffer is no longer driven. (8) these parameters depend on the clock jitter. these parameters are meas ured at stable clock. (9) output timing is measured by using normal driver strength. slew = (v ih min (ac) ? v il max (ac))/ ? t v ih min (ac) ? t v ref v il max (ac) v swing ? t v ss v ddq ac test load measurement point output v tt 25 ?
tc59lm913/05amb-50,-55 2004-08-20 12/52 rev 1.0 power up sequence (1) as for pd , being maintained by the low state ( 0.2 v) is desirable before a power-supply injection. (2) apply v dd before or at the same time as v ddq . (3) apply v ddq before or at the same time as v ref . (4) start clock (clk, clk ) and maintain stable condition for 200 s (min). (5) after stable power and clock, apply desl and take pd =h. (6) issue emrs to enable dll and to define driver strength. (note: 1) (7) issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note: 1) (8) issue two or more auto-refresh commands (note: 1). (9) ready for normal operation after 200 clocks from extended mode register programming. notes: (1) sequence 6, 7 and 8 can be issued in random order. (2) l = logic low, h = logic high clk command dq address v dd v ddq v ref clk pd 2.5v ( typ ) 2.5v ( typ ) 1.25v ( typ ) 200us ( min ) t pdex l pda l rsc l rsc l refc l refc 200clock c y cle ( min ) desl rda mrs desl rda mrs desl wra ref desl wra ref desl op-code emrs op-code mrs emrs mrs auto refresh cycle normal operation hi-z dqs
tc59lm913/05amb-50,-55 2004-08-20 13/52 rev 1.0 timing diagrams input timing timing of the clk, t t t ck clk v ih v il v ih v il t cl t ch t t v ih (ac) v il (ac) clk clk clk v x v x v x v id (ac) clk t ih t is t ih t ck t cl t ch cs dq (input) cl k clk refer to the command truth table. t ck 1st 2nd t is t ih t is t ih 1st 2nd t ih t is t ih ua, ba la t is t is fn a0~a13 ba0~ba2 t ds t dh t ds t dh dqs command and address data
tc59lm913/05amb-50,-55 2004-08-20 14/52 rev 1.0 read timing (burst length = 4) clk inpu t (control & addresses) dqs (output) dq (output) cas latency = 3 dqs (output) dq (output) cas latency = 4 note: dq0 to dq15 are aligned with dqs or ldqs/udqs. hi-z lal (after rda) t is t ih hi-z t ch t cl t ck hi-z hi-z t qsq t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac preamble postamble t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz preamble postamble q0 q1 q2 q3 t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 desl the correspondence of ldqs, udqs to dq. (tc59lm913amb) ldqs dq0 dq7 udqs dq8 dq15 cl k
tc59lm913/05amb-50,-55 2004-08-20 15/52 rev 1.0 write timing (burst length = 4) note: dq0 to dq15 are sampled at both edges of dqs or ldqs / udqs. dq (input) dqs (input) dq (input) cas latency = 4 dqs (input) cas latency = 3 t dspre t ds t dh d0 d1 t ds t dh d2 d3 t ds t dh t dss t dqss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d1 t ds t dh d3 t ds t dh t dss t dqss t dspreh t dsp t dsp preamble postamble t dsp t dss t dspres t dspst t dss t dspsth t dqss cl k clk inpu t (control & addresses) lal (after wra) t is t ih t ch t cl t ck t dspre desl the correspondence of ldqs, udqs to dq. (tc59lm913amb) ldqs dq0 dq7 udqs dq8 dq15 d0 d2
tc59lm913/05amb-50,-55 2004-08-20 16/52 rev 1.0 t refi , t pause , ixxxx timing inpu t (control & addresses) cl k clk command t is t ih note: ?i xxxx ? means ?i rc ?, ?i rcd ?, ?i ras ?, etc. t refi , t pause , i xxxx command t is t ih
tc59lm913/05amb-50,-55 2004-08-20 17/52 rev 1.0 write timing (x16 device) (burst length =4) cl k clk inpu t (control & addresses) ldqs dq0~dq7 cas latency = 3 udqs dq8~dq15 ldqs dq0~dq7 cas latency = 4 udqs dq8~dq15 preamble lal wra t ds postamble t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble postamble t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t dh t ds t ds preamble t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t ds desl postamble postamble t dh t dh
tc59lm913/05amb-50,-55 2004-08-20 18/52 rev 1.0 function truth table (notes: 1, 2, 3) command truth table (notes: 4) ? the first command symbol function cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 desl device deselect h rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ? the second command (the next clock of rda or wra command) symbol function cs fn ba1 ~ba0 ba2 a13 a12 ~a11 a10 ~a9 a8 a7 a6~a0 lal lower address latch (x16) h v v v la la lal lower address latch (x8) h v v la la la ref auto-refresh l mrs mode register set l v l l l l l v v notes: 1. l = logic low, h = logic high, = either l or h, v = valid (specified value), ba = bank address, ua = upper address, la = lower address 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latche d on the crossing point of diff erential clock input where clk goes to high. 4. operation mode is decided by the combination of 1st command and 2nd command. refer to ?state diagram? and the command table below. read command table command (symbol) cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h la la la 5 note 5 : for x16 device, a8 is ?x? (either l or h). write command table ? tc59lm913amb command(symbol) cs fn ba1~ ba0 ba2 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h lvw0 lvw1 uvw0 uvw1 la la ? TC59LM905AMB command(symbol) cs fn ba1~ ba0 ba2 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h vw0 vw1 la la la notes: 6. ba2, a13 ~ a11 are used for variable write length (vw) control at write operation.
tc59lm913/05amb-50,-55 2004-08-20 19/52 rev 1.0 function truth table (continued) vw truth table burst length function vw0 vw1 write all words l bl=2 write first one word h reserved l l write all words h l write first two words l h bl=4 write first one word h h note 7 : for x16 device, lvw0 and lvw1 control dq0~dq7. uvw0 and uvw1 control dq8~dq15. mode register set command table command (symbol) cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes rda (1st) l h mrs (2nd) l v v v v v 8 notes: 8. refer to ?mode register table?. auto-refresh command table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l auto-refresh ref (2nd) active h h l self-refresh command table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l self-refresh entry ref (2nd) active h l l 9, 10 self-refresh continue ? self-refresh l l self-refresh exit selfx self-refresh l h h 11 power down table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes power down entry pden standby h l h 10 power down continue ? power down l l power down exit pdex power down l h h 11 notes: 9. pd has to be brought to low within t fpdl from ref command. 10. pd should be brought to low after dq?s state turned high impedance. 11. when pd is brought to high from low, this function is executed asynchronously.
tc59lm913/05amb-50,-55 2004-08-20 20/52 rev 1.0 function truth table (continued) pd current state n ? 1 n cs fn address command action notes h h h desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h pden power down entry 12 h l l ? illegal idle l ? refer to power down state h h h la lal begin read h h l op-code mrs/emrs access to mode register h l h pden illegal h l l mrs/emrs illegal row active for read l ? invalid h h h la lal begin write h h l ref auto-refresh h l h pden illegal h l l ref (self) self-refresh entry row active for write l ? invalid h h h desl continue burst read to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal read l ? invalid h h h desl data write & continue burst write to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal write l ? invalid h h h desl nop idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden self-refresh entry 14 h l l ? illegal auto-refreshing l ? refer to self-refreshing state h h h desl nop idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden illegal h l l ? illegal mode register accessing l ? invalid h ? invalid l l ? maintain power down mode l h h pdex exit power down mode idle after t pdex power down l h l ? illegal h ? invalid l l ? maintain self-refresh l h h selfx exit self-refresh idle after i refc self-refreshing l h l ? illegal notes: 12. illegal if any bank is not idle. 13. illegal to bank in specified stat es; function may be legal in the bank inidicated by bank address (ba). 14. illegal if t fpdl is not satisfied.
tc59lm913/05amb-50,-55 2004-08-20 21/52 rev 1.0 mode register table regular mode register (notes: 1) address ba1 * 1 ba0 * 1 ba2, a13~a8 a7 * 3 a6~a4 a3 a2~a0 register 0 0 0 te cl bt bl a7 test mode (te) a3 burst type (bt) 0 regular (default) 0 sequential 1 test mode entry 1 interleave a6 a5 a4 cas latency (cl) a2 a1 a0 burst length (bl) 0 0 reserved * 2 0 0 0 reserved * 2 0 1 0 reserved * 2 0 0 1 2 0 1 1 3 0 1 0 4 1 0 0 4 0 1 1 1 0 1 reserved * 2 1 reserved * 2 1 1 0 reserved * 2 1 1 1 reserved * 2 extended mode register (notes: 4) address ba1 * 4 ba0 * 4 ba2, a13~a12 a11 a10~a7 a6 a5~a2 a1 a0 * 5 register 0 1 0 0 0 dic 0 dic ds a6 a1 output drive impedance control (dic) 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver a0 dll switch (ds) 0 dll enable 1 dll disable notes: 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. ?reserved? places in regular mode register should not be set. 3. a7 in regular mode register must be set to ?0? (low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combination of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation.
tc59lm913/05amb-50,-55 2004-08-20 22/52 rev 1.0 state diagram standby (idle) self- refresh power down pden ( pd = l) pdex ( pd = h) selfx ( pd = h) mode register auto- refresh active active (restore) read write (buffer) pd = l pd = h wra rda mrs ref command input lal a utomatic return the second command at active state must be issued 1 clock after rda or wra command input. lal
tc59lm913/05amb-50,-55 2004-08-20 23/52 rev 1.0 timing diagrams single bank read timing (cl = 3) cl k clk hi-z dq (output) bl = 2 i rc = = 3 command i rc = = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = = = = 4 cycles bank add. #0 #0 #0 dqs (output) hi-z dq (output) bl = 4 hi-z dqs (output) rda ua #0 cl = = 3 cl = 3 cl = = 3 q0 q1 q0 q1 q0 q2 q3 q2 q3 q1 q2 q0 q1 q0 q1 q0 q1
tc59lm913/05amb-50,-55 2004-08-20 24/52 rev 1.0 single bank read timing (cl = 4) cl k clk hi-z dq (output) bl = 2 i rc = = 4 command i rc = = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = = = = 4 cycles bank add. #0 #0 #0 dqs (output) cl = = 4 hi-z dq (output) bl = 4 hi-z q0 q1 cl = 4 dqs (output) cl = = 4 q2 q3 q2 q3 rda ua #0 q0 q1 q0 q1 q0
tc59lm913/05amb-50,-55 2004-08-20 25/52 rev 1.0 single bank write timing (cl = 3) cl k clk dqs (input) dq (input) bl = 2 i rc = 5 cycles wl = 2 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal desl wra lal wra lal desl desl i rc = 5 cycles address la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 d0 d1 dqs (input) dq (input) bl = 4 d0 d1 d2 d3 d0 d1 d0 d1 d0 d1 d2 d3 wra ua #0 wl = 2 wl = 2 wl = 2 wl = 2 wl = 2 d0 d1 d2 d3 ua
tc59lm913/05amb-50,-55 2004-08-20 26/52 rev 1.0 single bank write timing (cl = 4) cl k clk bl = 2 i rc = = 3 command i rc = = 5 c y cles address ua la ua la ua la bank add. #0 #0 #0 wl = = 3 bl = 4 wl = 3 wl = = 3 wra ua #0 wra dqs (input) dq (input) dqs (input) dq (input) d0 d1 d2 d3 d0 d1 d0 d1 d0 d1 d2 d3 d0 d1 d2 d3
tc59lm913/05amb-50,-55 2004-08-20 27/52 rev 1.0 single bank read-write timing (cl = 3) cl k clk dqs dq bl = 2 i r c = 5 c y cles hi-z q0 q1 cl = 3 command i rc = = 5 c y cles address ua la ua la ua la bank add. #0 #0 #0 wl = = 3 dqs dq bl = 4 hi-z wra ua #0 q0 q1 cl = 3 wl = = 3 hi-z hi-z q0 q1 d0 d1 q2 q3 d2 d3 q0 q1 q2
tc59lm913/05amb-50,-55 2004-08-20 28/52 rev 1.0 single bank read-write timing (cl = 4) cl k clk dqs dq bl = 2 i rc = 5 c y cles hi-z q0 q1 cl = 4 command i r c = = 5 c y cles address ua la ua la ua la bank add. #0 #0 #0 wl = = 4 dqs dq bl = 4 hi-z cl = 4 wl = = 4 wra ua #0 hi-z hi-z q0 q1 d0 d1 q0 q2 q3 d2 d3
tc59lm913/05amb-50,-55 2004-08-20 29/52 rev 1.0 multiple bank read timing (cl = 3) rda ua bank "b" cl k clk hi-z dq (output) bl = 2 i rbd = 2 cycles hi-z cl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" dqs (output) cl = 3 dq (output) bl = 4 hi-z dqs (output) rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles hi-z note: l rc to the same bank must be satisfied. i rbd = 2 cycles la cl = 3 cl = 3 qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 qd0 qd1 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qd0 qd1
tc59lm913/05amb-50,-55 2004-08-20 30/52 rev 1.0 multiple bank read timing (cl = 4) rda ua bank "b" cl k clk hi-z dq (output) bl = 2 i rbd = 2 cycles hi-z cl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" dqs (output) cl = 4 dq (output) bl = 4 hi-z dqs (output) rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles hi-z cl = 4 cl = 4 note: l rc to the same bank must be satisfied. i rbd = 2 cycles la qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1
tc59lm913/05amb-50,-55 2004-08-20 31/52 rev 1.0 multiple bank write timing (cl = 3) clk clk dqs (input) dq (input) bl = 2 wl = 2 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" wl = 2 dqs (input) dq (input) bl = 4 wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 dd0 dd1 wra ua bank "b" wl = 2 wl = 2 dd0 dd1
tc59lm913/05amb-50,-55 2004-08-20 32/52 rev 1.0 multiple bank write timing (cl = 4) clk clk dqs (input) dq (input) bl = 2 wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" wl = 3 dqs (input) dq (input) bl = 4 wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 wra ua bank "b"
tc59lm913/05amb-50,-55 2004-08-20 33/52 rev 1.0 multiple bank read-write timing (bl = 2) cl k clk dqs cl = 4 i rbd = 2 cycles wl = = = 1 cycle i rwd = 2 cycles i wrd = = = 3 wl = =
tc59lm913/05amb-50,-55 2004-08-20 34/52 rev 1.0 multiple bank read-write timing (bl = 4) cl k clk dqs cl = 4 i rbd = 2 cycles wl = = = 1 cycle i rwd = 3 cycles i wrd = = = 1 cycle dqs cl = 3 wl = = 3 dq hi - z qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qd2 qd3 hi - z hi - z
tc59lm913/05amb-50,-55 2004-08-20 35/52 rev 1.0 write with variavle write length (vw) control (cl = 4) cl k clk dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 2, sequential mode desl la=#1 vw=1 vw0 = low vw1 = don't care vw0 = high vw1 = don't care dq (input) d0 d0 d1 lower address #3 #2 #1 ( #0 ) last one data is masked. dqs (input) command wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 4, sequential mode desl la=#1 vw=1 dq (input) d0 d0 d1 lower address #3 #0 #1 ( #2 )( #3 )( #0 ) last three data are masked. desl wra lal vw0 = high vw1 = low vw0 = high vw1 = high ua la=#2 vw=2 vw0 = low vw1 = high bank "a" d2 d3 d0 d1 #1 #2 last two data are masked. ( #0 )( #1 ) #2 #3 note: dqs input must be continued till end of burst count even if some of laster data is masked.
tc59lm913/05amb-50,-55 2004-08-20 36/52 rev 1.0 power down timing (cl = 4, bl = 4) read cycle to power down mode cl k clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pd a t ih t is i pd = 1 cycle t pdex power down entry power down exit note: pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. command rda lal desl address ua ua desl rda or wra la l rc(min) , t refi(max) t qpdh dqs (output) hi-z q0 q1 cl = 4 q2 q3 hi-z dq (output) pd hi-z
tc59lm913/05amb-50,-55 2004-08-20 37/52 rev 1.0 power down timing (cl = 4, bl = 4) write cycle to power down mode cl k clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pd a t ih t is i pd = 1 cycle t pdex note: pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. command wra lal desl address ua ua desl rda or wra la l rc(min) , t refi(max) dqs (input) wl = 3 d0 d1 d2 d3 dq (input) pd 2 clock cycles wl = 3
tc59lm913/05amb-50,-55 2004-08-20 38/52 rev 1.0 mode register set timing (cl = 4, bl = 2) from read operation to mode register set operation. cl k clk dqs (output) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl a13~a0 ua valid (opcode) i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="0" ba1="0" ba2="0" ba lal dq (output) cl + bl/2 q0 q1 note: minimum delay from lal following rda to rda of mrs operation is cl+bl/2. 15 la hi-z
tc59lm913/05amb-50,-55 2004-08-20 39/52 rev 1.0 mode register set timing (cl = 4, bl = 4) from write operation to mode register set operation. cl k clk dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl a13~a0 ua valid (opcode) i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="0" ba1="0" ba2="0" ba d0 d1 d2 d3 dq (input) 15 wl+bl/2 la lal note: minimum delay from lal following wra to rda of mrs operation is wl+bl/2.
tc59lm913/05amb-50,-55 2004-08-20 40/52 rev 1.0 extended mode register set timing (cl = 4, bl = 2) from read operation to extended mode register set operation. cl k clk dqs (output) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl a13~a0 ua valid (opcode) i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="1" ba1="0" ba2="0" ba dq (output) cl + bl/2 q0 q1 note: minimum delay from lal following rda to rda of emrs operation is cl+bl/2. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. 15 la lal hi-z
tc59lm913/05amb-50,-55 2004-08-20 41/52 rev 1.0 extended mode register set timing (cl = 4, bl = 4) from write operation to extende d mode register set operation. cl k clk dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl a13~a0 ua valid (opcode) wl+bl/2 i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="1" ba1="0" ba2="0" ba d0 d1 d2 d3 dq (input) note: dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. minimum delay from lal following wra to rda of emrs operation is wl+bl/2. 15 lal la
tc59lm913/05amb-50,-55 2004-08-20 42/52 rev 1.0 auto-refresh timing (cl = 4, bl = 4) cl k wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = ? 1n n + 1 n + 2 rda lal q0 hi-z q1 hi-z cl = 4 command i rc = 5 cycles desl rd a or wr a lal o r mrs or ref i rcd = 1 cycle note: in case of cl = 4, i refc must be meet 18 clock cycles. when the auto-refresh operation is performed, the synt hetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refr esh cycles that is sampled randomly. wra ref i refc = 18 cycles hi-z i ras = 4 cycles i rcd = 1 cycle q2 q3 desl bank, ua la bank, address hi-z
tc59lm913/05amb-50,-55 2004-08-20 43/52 rev 1.0 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the fi rst clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . cl k clk hi-z dqs (output) dq (output) 0 1 2 m ? 1mm + 1m + 2 hi-z command i lock t pdex i pd a = 1 cycles * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command (1st) * 6 command (2nd) * 6 i rcd = * 2 i refc i refc i rcd = ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd i ckd t qpdh auto refresh self refresh entry
tc59lm913/05amb-50,-55 2004-08-20 44/52 rev 1.0 functional description network fcram tm fcram tm is an acronym of fast cycle ra ndom access memory. the network fcram tm is competent to perform fast random core access, low latency and high-speed data transfer. pin functions clock inputs: clk & the clk and clk inputs are used as the reference for synchron ous operation. clk is ma ster clock input. the cs , fn and all address input signals are sampled on the cro ssing of the positive edge of clk and the negative edge of clk . the dqs and dq output are aligned to the crossing point of clk and clk . the timing reference point for the differential clock is when the clk and clk signals cross during a transition. power down: the pd input controls the entry to the power down or self-refresh modes. the pd input does not have a clock suspend function like a cke inpu t of a standard sdrams, ther efore it is illegal to bring pd pin into low state if any read or write operation is being performed. chip select & function control: & fn the cs and fn inputs are a control signal fo r forming the operation commands on fcram tm . each operation mode is decided by the combination of the two consecutive operat ion commands using the cs and fn inputs. bank addresses: ba0~ba2 the ba0 to ba2 inputs are latched at the time of asse rtion of the rda or wra command and are selected the bank to be used for the operation. ba0 and ba1 also define which mode register is loaded during the mode register set command (mrs or emrs). ba0 ba1 ba2 bank #0 0 0 0 bank #1 1 0 0 bank #2 0 1 0 bank #3 1 1 0 bank #4 0 0 1 bank #5 1 0 1 bank #6 0 1 1 bank #7 1 1 1 also, when ba2 input assign to a14 input, tc59lm913/05amb can function as 4bank devices and can keep backward compatibility to 25 6mb(4bank) network fcram. address inputs: a0~a13 address inputs are used to access th e arbitrary address of the memory cell array within each bank. the upper addresses with bank addresses are latched at the rda or wra command and the lowe r addresses are latched at the lal command. the a0 to a13 inputs are also used fo r setting the data in the regular or extended mode register set cycle. i/o organization upper address lower address 8 bits a0~a13 a0~a8 8 bank operation 16 bits a0~a13 a0~a7 8 bits a0~a13, ba2(a14) a0~a8 4 bank operation 16 bits a0~a13, ba2(a14) a0~a7 clk pd cs
tc59lm913/05amb-50,-55 2004-08-20 45/52 rev 1.0 data input/output: dq0~dq7 or dq15 the input data of dq0 to dq15 are take n in synchronizing with the both edges of dqs in put signal. the output data of dq0 to dq15 are outputted synchron izing with the both edges of dqs signal. data strobe: dqs, ldqs / udqs the dqs is bi-directional signal. both edge of dqs are used as the referenc e of data input or output. in write operation, the dqs used as an input si gnal is utilized for a latch of write da ta. in read operation, the dqs is an output signal provides the read data strobe. power supply: v dd , v ddq , v ss , v ssq v dd and v ss are power supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage: v ref v ref is reference voltage for all input signals.
tc59lm913/05amb-50,-55 2004-08-20 46/52 rev 1.0 command functions and operations tc59lm913/05amb are introduced the two consecutive command input meth od. therefore, except for power down mode, each operation mode decided by the combinat ion of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper a ddresses to the idle bank puts the bank designated by bank address in a read mode. when the lal command wi th lower addresses is issued at the next clock of the rda command, the data is re ad out sequentially synchronizing with the both edges of dqs output signal (burst read operation). the initial valid read data appears after cas latency from the issuing of the lal command. the valid data is outputted for a burst length. the cas latency, the burst length of read data and the burst type must be set in the mode register beforehand. the read operated bank goes back auto matically to the idle state after l rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal command wi th lower addresses is issued at the next clock of the wra command, the input data is latched sequentially synchronizing wi th the both edges of dqs input signal (burst write operation). the data an d dqs inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal command. the dqs has to be provided for a burst length. the cas latency and the burst type must be set in the mode register beforehand. the write operated bank g oes back automatically to the idle state after l rc . write burst length is controlled by vw0 and vw1 inputs with lal command. see vw truth table. auto-refresh operation (1st command + 2nd command = wra + ref) tc59lm913/05amb are required to refresh like a standard sdram. the auto-refresh operation is begun with the ref command following to the wra command. the auto-ref resh mode can be effective only when all banks are in the idle state. in a point to notice, the write mode started with the wra command is canceled by the ref command having gone into the next clock of the wra co mmand instead of the lal co mmand. the minimum period between the auto-refresh command and the next command is specified by l refc . however, about a synthetic average interval of auto-refresh command, it must be care ful. in case of equally dist ributed refresh, auto-refresh command has to be issued within once for every 3.9 s by the maximum. in case of burst refresh or random distributed refresh, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles that can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with = ?l?) in case of self-refresh operation, re fresh operation can be performed automatically by using an internal timer. when all banks are in the idle state and all outputs are in hi-z states, the tc59lm913/05amb become self-refresh mode by issuing the self-refresh command. pd has to be brought to ?low? within t fpdl from the ref command following to the wra command for a self-refresh mode entry. in order to satisfy the refresh period, the self-refresh entry command sh ould be asserted within 3.9 s after the latest auto-refresh command. once the device enters self-refresh mode, the desl command must be continued for l refc period. in addition, it is desirable that clock input is kept in l ckd period. the device is in self-refresh mode as long as pd held ?low?. during self-refresh mode, all input and output buffers are disabled except for pd , therefore the power dissipation lowers. regarding a self-refresh mode exit, pd has to be changed over from ?low? to ?high? along with the desl command, and the desl command has to be continuously issued in the number of clocks specified by l refc . the self-refresh exit function is asynchro nous operation. it is required that one auto-refresh command is issued to avoid the violation of the refresh period just after l refc from self-refresh exit. power down mode ( = ?l?) when all banks are in the idle state and dq outputs are in hi-z states, the tc59lm913/05amb become power down mode by asserting pd is ?low?. when the device enters the po wer down mode, all input and output buffers are disabled after specified time except for pd . therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to ?high? and the desl comm and has to be issued for two clocks cycle after pd goes high. the power down exit function is asynchronous operation. pd pd
tc59lm913/05amb-50,-55 2004-08-20 47/52 rev 1.0 mode register set (mrs) and extended mode register set (emrs) (1st command + 2nd command = rda + mrs) when all banks are in the idle stat e, issuing the mrs command following to the rda command can program the mode register. in a point to notice, the read mode started with the rda comman d is canceled by the mrs command having gone into the next clock of the rda command instead of the lal command. the data to be set in the mode register is transferred using a0 to a14, ba0 to ba1 address inputs. the tc59lm913/05amb have two mode registers. these are regular and extended mode regi ster. the regular or extended mode register is chosen by ba0 and ba1 in the mrs command. the regular mode register designates the operation mode for a read or write cycle. the regular mode regi ster has four function fields. the four fields are as follows: (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has three function fields. the three fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver im pedance control field. (e-3) dqs enable field. once those fields in the mode register are set up, the re gister contents are maintained until the mode register is set up again by another mrs command or power supply is lo st. the initial value of the regular or extended mode register after power-up is undefined, therefore the mode register set command must be issued before proper operation. ? regular mode register/extended mode register change bits (ba0, ba1). these bits are used to choose eith er regular mrs or extended mrs ba1 ba0 mode register set 0 0 regular mrs 0 1 extended mrs 1 reserved regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access usin g the a2 to a0 pins and sets the burst length to be 2 or 4 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 reserved 1 reserved (r-2) burst type field (a3) the burst type can be chosen interleave mode or sequen tial mode. when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interleave mode is selected. both burst types support burst length of 2 and 4 words. a3 burst type 0 sequential 1 interleave
tc59lm913/05amb-50,-55 2004-08-20 48/52 rev 1.0 ? addressing sequence of sequential mode (a3) a column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. addressing sequence for sequential mode data access address burst length data 0 n data 1 n + 1 data 2 n + 2 data 3 n + 3 2 words (address bits is la0) not carried from la0~la1 4 words (address bits is la1, la0) not carried from la1~la2 ? addressing sequence of interleave mode a column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode data access address burst length data 0 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 1 ??? a8 a7 a6 a5 a4 a3 a2 a1 0 a data 2 ??? a8 a7 a6 a5 a4 a3 a2 1 a a0 data 3 ??? a8 a7 a6 a5 a4 a3 a2 1 a 0 a 2 words 4 words (r-3) cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the lal command following the rda command to the first data read. the minimum values of cas latency depends on the frequency of clk. in a write mode, the place of clock th at should input write data is cas latency cycles ? 1. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved (r-4) test mode field (a7) this bit is used to enter test mode for supplier only and must be set to ?0? for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a13, ba2) these bits are reserved for future operations. th ey must be set to ?0? for normal operation. cl k clk command dqs dq data 0 data 1 data 2 data 3 rda lal cas latency = 4
tc59lm913/05amb-50,-55 2004-08-20 49/52 rev 1.0 extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is se t ?0?, dll is enabled. this bit must be set to ?0? for normal operation. (e-2) output driver impeda nce control field (a1, a6) this field is used to choose outp ut driver strength. four types of driver strength are supported. a6 a1 output driver impedance control 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver (e-3) dqs enable (a10) dqs is not supported. this bit must be always set ?0?. (e-4) reserved field (a2 to a5, a7 to a9, a11 to a13, ba2) these bits are reserved for future operations and must be set to ?0? for normal operation.
tc59lm913/05amb-50,-55 2004-08-20 50/52 rev 1.0 package dimensions 0.2 s b 0.2 s a 0.08 s ab 13.086 0 -0.15 16.5 10.975 0 -0.15 12.7 0.15 0.1 0.2 s 0.15min 1.20max 0.4 0.05 1.5 1.5 123 456 index r p n m l k j h g f e d c b a 1.0 2.0 1.25 3.85 3.85 1.85 1.0 a b s s 0.5 0.05 p-bga64-1317-1.00az note: in order to support a package, four outer balls located on f and k row are required to assembly to board. these four ball is not connected to any electrical level. weight: 0.23g (typ.)
tc59lm913/05amb-50,-55 2004-08-20 51/52 rev 1.0 revision history ? rev.0.9 (feb. 27 ?2004) ? rev0.91 (mar. 16 ?2004) ? corrected typo(page50). pin name is changed from ?q? to ?r?. ? rev0.92 (apr. 21 ?2004) ? i dd6 spec changed from 20ma to 40ma (page 1, 7). ? i dd5b spec changed as below (page 7). ? ? 50?: 250ma 420ma, ? ? 55?: 240ma 400ma, ? ? 60?: 230ma 380ma ? corrected typo (page 7). cas latency condition is changed from cl5 to cl4. ? rev0.93 (jun. 9 ?2004) ? auto-refresh average interval (t refi ) changed from 7.8 s to 3.9 s (page 1, 10, 46). ? i dd6 spec changed from 40ma to 20ma (page 1, 7). ? i dd5b spec changed as below (page 7). ? ? 50? : 420ma 250ma, ? ? 55?: 400ma 240ma, ? ? 60?: 380ma 230ma ? rev1.0 (aug. 20 ?2004) ? ?-60? version dropped. ? package name (p ? bga64 ? 1317 ? 1.00az) added (page 1). ? some note in the page 8 moved to page 7 (page 7, 8). ? note 2 changed as below (page 7). before: these parameters depend on the output load ing. the specified values are obtained with the output open. after: these parameters define the current between vdd and vss. ? corrected typo (page 14, 15, 17). ? package weight (0.23g) added (page 50).
tc59lm913/05amb-50,-55 2004-08-20 52/52 rev 1.0 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshi ba products specifications. also, pl ease keep in mind the precautions and conditions set forth in the ?handling guide for semicond uctor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which are prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

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